The present invention relates to processes for fabricating semiconductor devices and, more particularly, to a semiconductor fabrication process in which a buried layer is formed.
In semiconductor devices such as semiconductor integrated circuits, a p+ buried layer is provided for the application of an “up-down isolation” technique. In up-down isolation, an region is not only diffused downwardly from the surface of an epitaxial layer but also is rediffused upwardly from below the epitaxial layer, i.e., from the substrate side. With this technique, the diffusion time is shortened so as to suppress the lateral spread of the isolation (p-diffusion). Accordingly, the chip area can be reduced and, at the same time, the breakdown voltage of the completed semiconductor device is increased because of limited upward diffusion of the n+ region.
Taking an npn transistor as an example of a semiconductor device having a buried layer, a first related process sequence for forming the buried layer in this transistor is described hereinafter with reference to FIGS. 1 through 4. In step 1 shown in FIG. 1, a p-type substrate 11 typically made of silicon is provided with an oxide film mask 12, such as an SiO2, film, arranged so that the surface of the substrate 11 is exposed in a region where the buried layer is to be formed. The surface of the region of the substrate 11 which is not covered with the mask 12 may be referred to as a window W.
In the next step 2 shown in FIG. 2, the substrate 11 is put into a diffusion furnace, and ions of a p-type impurity such as boron (B) are implanted into the substrate 11 through the window W to form an ion-implanted region 13 in the substrate 11.
In step 3 shown in FIG. 3, the entire substrate 11 is heated to a temperature of about 800 to 1300° C. in an oxidizing atmosphere such as dry oxygen or water vapor. Through the annealing process, the p-type impurity is activated and diffused into the substrate 1 form a p+ diffusion region 14′ beneath the window W. During this diffusion, an oxide film 15, such as an SiO2, film, is also formed in the window W of the substrate 11.
In step 4 shown in FIG. 4, the SiO2 mask 12 and the oxide film 15 are removed to expose the p+ diffusion region 14′ in the window W, so that a p+ buried layer 14 is formed. Upon removal of the oxide film 15, a step 14a will form at the edge of the p+ buried layer 14 which corresponds to the periphery of the window W.
The thus fabricated semiconductor is subjected to the further treatment to provide an npn transistor. For example, the substrate 11 is put in an epitaxial growth furnace, an epitaxial layer 16 is grown on the surface of the substrate 11 as in step 5 in FIG. 5.
FIG. 6 is a graphical representation of impurity concentration distribution profiles in the respective steps in the process of fabricating the buried layer. In the graph, the abscissa represents depth measured from the surface of the substrate, and the ordinate, impurity concentration. In the graph, “a” is an impurity concentration distribution when impurity ions are implanted in the step 2. In the step 3, the impurity region is expanded to profile an impurity concentration distribution indicated by “b”. In the step 4, the impurity is further diffused to form a profile of an impurity concentration distribution indicated by “c”. By etching process, the surface of the substrate surface is lowered to a level indicated by z0.
In the fabrication process, the impurity diffusion caused by the heat treatment in the gas etching process reaches the substrate surface. Therefore, if the substrate is subjected to the epitaxial growing process, an undesirable phenomenon of autodoping from the buried layer 14 to the epitaxial layer 16 occurs as shown in FIG. 7. In the figure, character “z0” indicates an interface between the epitaxial layer 16 and the p+ buried layer 14.
In the related process sequence described above, the buried layer 14 is formed by first performing ion implantation in step 2 (FIG. 2), then heating the substrate in step 3 (FIG. 3). However, the ion implantation performed in step 2 will cause significant damage to the surface of the substrate 11 in the window W. If the substrate is heated in the next step 3 to form the p+ diffusion region 14′ without repairing the surface damage, surface defects will appear in the p+ buried layer 14 when it is formed by exposing the p+ diffusion region 14′ in step 4 (FIG. 8). This is undesired from a practical viewpoint since those surface defects will lead to structural defects in the final transistor device.
In the related semiconductor fabrication process, the substrate is annealed in an oxidizing atmosphere. This sometimes gives rise of crystal defects, e.g., OSF (oxide-induced stacking fault), in the substrate surface. In case where an epitaxial layer is formed on the substrate surface suffering from crystal defects, the resultant epitaxial layer is deteriorated in its film quality since it is adversely affected by the crystal defects. As a result, the final transistor device as a product suffers from structural defects.
Also in the related fabrication process, the furnace used by the annealing step is different from that by the epitaxial growing step. Therefore, the substrate undergoes a temperature variation cycle of temperature rise and fall (up to room temperature), which takes place when it is taken out of a furnace and put into another furnace. The thermal stress, which is caused in the substrate at this time, becomes a factor to cause crystal defects in the substrate. The epitaxial layer grows while orientating crystal axis thereof with that at the substrate surface. A surface state of the substrate before the epitaxial layer growing process step starts, greatly affects the film quality of the growing layer.
The temperature variation cycle possibly causes elongation of the fabricating time and unnecessary complexity of the fabrication process.
A second related process of fabricating a semiconductor device in which the annealing step 3 in the semiconductor fabrication process mentioned above is executed by use of the energy beam, is disclosed in Unexamined Japanese Patent Publication No. Sho. 57-106046. The other fabricating steps than the annealing step are substantially the same as in the above-mentioned fabrication process. The unique feature of the fabrication process of the publication resides in that the impurity is activated without greatly varying the impurity concentration distributions profiled after the ion implantation. In this fabrication process, the impurity concentration distributions in the respective fabricating steps are profiled as shown in FIG. 8. In the figure, “a” is an impurity concentration distribution profile after the ion implantation; “b” is an impurity concentration distribution profile after the annealing; and “c” is an impurity concentration distribution profile after the gas etching. An impurity concentration is distributed, as shown in FIG. 9, in the substrate after the epitaxial growing step ends.
Where this fabrication process is used, no autodoping problem arises, but the crystal defects, e.g., OSF, induced in the annealing step performed in the oxidizing atmosphere inevitably occurs. In this respect, the problems arising from the crystal defects remain unsolved. Additionally, the substrate temperature inevitably varies when the substrate is taken out of the furnace and put into another furnace in the transient period from the annealing step to the epitaxial growing step. Therefore, the substrate surface serving as the epitaxial growing surface is thermally stressed, viz., the thermal stress problem remains unsolved.